The semiconductor industry runs on a cost curve that used to be predictable and no longer is. For decades, Moore’s Law meant that each new process node roughly halved cost-per-transistor — you got more compute for less money, like clockwork. That ended around 2015. TSMC’s N3 is more expensive per transistor than N5 for many designs. N2, the first GAA (gate-all-around) node, will be even worse. The transistors keep shrinking, but the economics have inverted: leading-edge silicon now costs more per transistor, not less.
This changes everything about who builds what. When a single EUV lithography machine costs $380M and a leading-edge fab costs $20B+, the number of companies that can play at the frontier keeps shrinking. TSMC, Samsung, Intel — that’s it for logic below 7nm, and TSMC has 90%+ market share for the AI chips that matter. The foundry dynamics are essentially a monopoly with two aspiring competitors, and the capacity allocation decisions TSMC makes — how many N4P wafer starts go to NVIDIA vs. Apple vs. AMD — shape the entire AI hardware landscape downstream.
Packaging is where the real action is now. CoWoS (chip-on-wafer-on-substrate) is the bottleneck for every high-end AI chip, because it’s what lets you attach 8 stacks of HBM3e to a GPU die. TSMC’s CoWoS capacity has been the binding constraint on B200 shipments, not the logic dies themselves. The notes below dig into these economics — what the N2 transition actually costs, who benefits, and why advanced packaging might matter more than the transistor node for the next decade.
- TSMC N2 Economics — GAA transition, cost-per-transistor, customer allocation